It always displays the first bit and then fills up the rest of the bits with don't cares (X). Here we have three inputs A, B, Cin and two outputs Sum, Cout. The Full Adder has three input states and two output states. The problem is that the output is not showing correctly. A Full Adder is a combinational circuit that performs an addition operation on three 1-bit binary numbers. Output cout, //carry will be sent as OP, but won't be further used.įullAdder mg0(.a_(a).
Here's the code for the single full adder: module FullAdder(Īssign cout_ = ((a_ & b_) | (b_ & cin_) | (cin_ & a_)) Īnd here's the code for the 8 bit adder modue which will call the full adder 8 times. That 8 bit adder should add 2 incoming inputs each of 8 bit bus. I'm writing a Verilog code to construct an 8 bit adder using 8 full adder.
